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Description: Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)
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Size: 7183360 |
Author: 独白惠茹 |
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Description: 1. understand how to improve CPU performance
2. master the working principle of pipelined MIPS microprocessor.
3. understand the concept of data adventure, control risk and the solution of pipeline conflict.
4. mastering the testing method of pipelined MIPS microprocessor(this file contains 3 packs,which is developed in Xilinx ISE
contain the basic functions of a typical CPU
5 stages:IF,ID,EX,MEM,WB
for education only)
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Size: 633856 |
Author: D.FRANCIS |
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Description: dds算法，调用xilinx IP ，ise(DDS algorithm, call Xilinx IP, ISE)
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Size: 5728256 |
Author: 阿士大夫 |
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Description: In this paper, a FPGA-based step motor driver implementing adjustable subdivision and sine pulse width modulation is introduced. This driving system can solve the high subdivision problem, increase the driving torque and angle resolution, and smooth the motor angle. Employing the bottom-top design method, the circuit was described by the VHDL language, synthesized by Xilinx ISE integrated environment, and simulated by Modelsim in both behavior level and gate level through the PLI interface. According to experiment’s result, this driver has the advantages of easy debugging, high anti-interference ability, larger driving power, low volume and low cost in large scale production.
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Size: 623104 |
Author: jionad123 |
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